1. Field of the Invention
The present invention relates to a reconfigurable processor and a reconfiguration method executed by the reconfigurable processor.
2. Description of the Related Art
In recent years, there has been an increasing demand for a technique for shortening an LSI design period, i.e. time taken to complete the design of an LSI. With an increase in the demand, attention is being given to the use of a dynamically reconfigurable device as one solution to the demand for shortening the LSI design period. The dynamically reconfigurable device is an LSI that incorporates a plurality of processing units (processing elements) each having an arithmetic logic unit (ALU), such that ALU control in each processing unit and connections between the processing units can be dynamically switched to different ones (during the operation of the LSI).
The dynamically reconfigurable device dynamically switches between circuits during execution of an application, thereby making the same LSI thereof compatible with a plurality of applications. The dynamically reconfigurable devices is typified by a DAPDNA and a DRP. Both the DAPDNA and the DRP incorporate hundreds of processing elements to thereby maintain high processing performance.
There have been proposed various techniques related to the dynamically reconfigurable device (see U.S. Patent Publication No. 2005/0038550).
In general, an LSI incorporates an error detector circuit for identifying the cause of an error, so as to cope with occurrence of a fault (error) during execution of an application by the LSI manufactured. This enables, even if an error occurs during execution of the application, the LSI to detect the error immediately, and perform maintenance suitable for the identified cause of the error. If the error having occurred is fatal, the LSI is replaced by a new one, whereas if the error is not fatal, a countermeasure is taken e.g. for continuing processing with reduced performance.
However, the conventional dynamically reconfigurable device is not provided with an error detecting means. For this reason, when an error occurs in the dynamically reconfigurable device during execution of an application by the LSI, it is impossible to detect the error immediately. This is fatal when the dynamically reconfigurable device is used for a mission critical system (i.e. a backbone system requiring high reliability and fault tolerance). Further, since the dynamically reconfigurable device is not provided with an error detecting means, even when an error that is not fatal occurs, it is required to replace the LSI with a new one, which causes an increase in cost.